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Does your VIP need a GUI?

b'Remember the days of internet text browsers? There were no pictures, video clips or even colorful fonts to catch the users’ eye. Users had to read through lines and lines of plain text just to find a...

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USB 3.0 Cheat Sheet

b'USB technology is one of the most popular and dominant technologies. There are three different generations of USB technology (USB 1.1, USB 2.0 and USB 3.0) that are prevalent with an update (USB 3.1)...

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OOPs! 3 Issues That Show System Verilog Threads are Not OOP Safe!

b'Verilog has a very limited and simple hierarchy. All processes are present in static modules. In some ways, System Verilog extends this concept of hierarchy with the support for dynamic data type of...

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How to become a Debug Ninja!

b'Please raise your hand, if you have ever felt like putting a fork in your left eye due to debugging issues. Below is an attempt to ensure that feeling never comes back, and pave way for you to become...

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VIP Factory: Applying Design Patterns For Boosting Test Bench Productivity

b'UVM verification methodology & System Verilog have become the de-facto standard for IP level functional verification. At Arrow Devices we have created multiple complete and customizable...

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USB 3.1 Cheat Sheet

b'Remember your engineering days in college when you were asked to bring a "cheat sheet" with all the formulas and concepts you could cram on a little piece of paper? It was a life saviour during exams...

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Functional Verification Basics: UVM Tutorial

b'UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry.  UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence,...

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UVM Sequences Tutorial

b'To verify an RTL design, you must define a stimulus (i.e. what kind of data should be sent to the DUT). In any test-bench environment, the driver is responsible for signal activities at the bit...

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USB3.1 Device DUT: 6 BiGGEST Verification Challenges

b'USB3.1 is the latest update to USB3.0. In the following blog, we describe the major changes which pose a verification challenge for USB3.1 Device DUT implementation. This will act as a ready reckoner...

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SoC Debug Made Easy!

b'With increasing complexity in today’s SoC designs, logic verification is one hurdle that all designers are eager to overcome. A majority of the verification effort is spent on debug. This is because...

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MIPI MPHY Cheat Sheet

b'In this blog, we provide you a ready reckoner Cheat Sheet to MIPI MPHY! With this cheat sheet, you can quickly refer to the key features and specifications of the MIPI MPHY protocol and get an...

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JEDEC UFS Cheat Sheet

b'Developing JEDEC UFS IP or Verification solution? Here is a ready reckoner cheat sheet that you can pin up on your cubicle!Background of JEDEC UFS:Universal Flash Storage (UFS) is a simple, high...

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USB Power Delivery Cheat Sheet

b'Are you developing USB-Power Delivery IP/VIP?In that case, does going through the spec every now and then seems tedious? The naswer to your prayers is here! This USB-Power Delivery Cheat Sheet...

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How to make your Waveform viewer SMART!

b'In this blog, we will look at how the Arrow Devices' Protocol Debug Analyzer (PDA) tool can analyze Signal Dump files and provide transaction and other higher abstraction views. We will explore how...

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Video: Make your waveform viewer decode protocols!

Engineers are spending a lot of time in looking at waveforms and manually decoding protocols to figure out bug scenarios. This process is tedious and time consuming. Have a look at the below video to...

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How to do a Protocol level Diff/Compare

b'Ok, so I ran my regression tests after making a few minor RTL changes and guess what?! Some tests failed! They were passing and now they fail! Aargh! Wish I had a quick way to compare the passing and...

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News Flash: Software engineers can debug hardware too!

b'Lets face it, timelines are shrinking with every successive project. What took 18 months earlier is expected in 12 months now. Derivative projects that took 6-9 months are expected to finish in 3-4...

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3 Reasons Why Verification Engineers should use Python instead of Perl

b'After many years of writing design verification automation scripts in Perl, we at Arrow Devices made a conscious decision to shift to Python, lock, stock and barrel. Scripting in Perl has multiple...

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9 interface protocol cheat-sheets to make your Design/Verif/Debug tasks easy!

b'This Christmas & New Year season, we present you with a few cheat-sheets that can help you design, verify and debug FASTER! This gift is SHARABLE! Please FORWARD and SHARE on LinkedIn with...

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Is it possible to develop high-performance EDA tools in Python?

b'With every generation, chips have become more complex and transistor counts have increased exponentially (according to the famous Moore’s Law). This exponential growth in complexity and size has led...

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